1. Field of the Invention
The present invention relates generally to arbiter circuits and, more particularly, to an arbiter circuit in which a metastable state is removed.
2. Description of the Background Art
In case that a plurality of digital subsystems (e.g., a multiprocessor system) which operate asynchronously to one another, share one resource (e.g., a disk unit), since requests-to-use a shared resource from the subsystems occur at random in time, a contention of these requests need be arbitrated. For example, when the request to use the shared resource is given from one of the subsystems while the shared resource is already in use by another subsystem, it is required to queue the request until the use of the shared resource is completed. An arbiter circuit carries out such contention arbitrating processing. The arbiter circuit is employed also to a DRAM (Dynamic Random Access Memory), one of semiconductor memory devices.
FIG. 6 is a schematic block diagram of one example of the configuration of a DRAM chip. Referring to this figure, the DRAM chip 13 comprises thereon a memory portion 14 having a plurality of storage elements and storing information, a memory control portion 15 for writing into and reading out from the memory portion 14 the information, a refresh control portion 16 for holding information stored in the memory portion 14, and an arbiter circuit 17 for preventing simultaneous operations of writing into and reading from the memory portion 14 by the memory control portion 15 and of holding the stored information of the memory portion 14 by the refresh control portion 16. The memory control portion 15 designates an address of a storage element to be accessed to the memory portion 14 in accordance with an access request externally supplied to the memory portion 14. Accordingly, the stored information of the designated storage element is read out from the memory portion 14 to be externally outputted, or alternatively, data externally supplied is stored in the designated storage element.
Meanwhile, each storage element of the memory portion 14 comprises a MOSFET (MOS Field Effect Transistor), and a charge stored in a gate thereof in accordance with the stored information is discharged from the gate and drain as time passes. That is, the stored information of the memory portion 14 of the DRAM disappears as the time passes. Thus, in order to avoid the disappearance of the stored information, the stored information is regularly rewritten in all the storage elements included in the memory portion 14. The refresh control portion 16 is a circuit to accomplish this rewriting. The refresh control portion 16 carries out the rewriting of the stored information regularly and automatically for the memory portion 14. As described above, the external access operation and the refresh operation from the refresh control portion 16 for the memory portion 14 are carried out in the DRAM. However, if these two operations are simultaneously carried out for the memory portion 14, these operations are not carried out correctly. For example, if the access operation is carried out in accordance with an external request while the refresh operation is being carried out for the memory portion 14, neither correct reading nor writing is carried out. Therefore, the access operation should not be carried out before completion of the refresh operation in such a case. Conversely, as a matter of course, the refresh operation should not be carried out before completion of the access operation in case that the access operation is previously carried out. That is, only the alternative of the access operation or the refresh operation need be acknowledged. The arbiter circuit 17 arbitrates such a contention between the request for the access operation and the one for refresh operation. When a access request is externally given to the memory portion 14, the memory control portion 15 first outputs an access request signal REQA to the arbiter circuit 17. Similarly, when the refresh operation should be carried out for the memory portion 14, the refresh control portion 16 first outputs a refresh request signal REQB to the arbiter circuit 17. The arbiter circuit 17 outputs an acknowledge signal which acknowledges only one of these request signals and a signal which does not acknowledge the other request signal to arbitrate the contention of these request signals. As a result, the control portion (the memory control portion 15 or the refresh control portion 16) supplied with the acknowledge signal carries out a predetermined operation for the memory portion 14. That is, when the acknowledge signal ACKA attains a voltage level indicating the acknowledgement, the external access operation is carried out for the memory portion 14. Meanwhile, when the other acknowledge signal ACKB attains a voltage level indicating the acknowledgement, the stored information is rewritten for the memory portion 14.
FIG. 7 is a logic circuit diagram of a conventional arbiter circuit shown in "ISSCC85 DIGEST OF TECHNICAL PAPERS (P.45)". Referring to this figure, this arbiter circuit comprises two-input NAND gates 1a and 1b. The arbiter circuit further comprises a request signal input terminal T1 to which a request signal REQ-A is inputted, a request signal input terminal T2 to which a request signal REQ-B is inputted, an acknowledge signal output terminal T3 from which an acknowledge signal ACK-A is derived in response to the request signal REQ-A, and an acknowledge signal output terminal T4 from which an acknowledge signal ACK-B is derived in response to the request signal REQ-B. The NAND gate 1a has one input terminal 1 connected to the input terminal T1 and the other input terminal 2 connected to an output terminal of the NAND gate 1b. Further, the NAND gate 1b has one input terminal 4 connected to the input terminal T2 and the other input terminal 3 connected to an output terminal of the NAND gate 1a. The respective output terminals of the NAND gates 1a and 1b are connected to the respective output terminals T3 and T4. A description on the NAND gates will be given prior to a description on the operation of this arbiter circuit. In general, a NAND gate of n-input one-output (n.gtoreq.2) carries out an inverter operation for the lowest input voltage out of n input voltages. That is, the NAND gate is constituted by a series connection of an AND gate and an inverter circuit.
FIG. 8 shows a transmission characteristic of a general NAND gate. The abscissa in this figure indicates an input voltage V.sub.IN, and the ordinate indicates an output voltage V.sub.OUT. Referring to this figure, if the lowest input voltage out of the n input voltages of the NAND gate is lower than an input voltage by which an output voltage level of the inverter circuit (H or L (logical high or logical low)) is switched, i.e., an input logic threshold voltage, a voltage of the H level is outputted by the inverter circuit. Conversely, if a minimum value of the n voltages to be inputted to the NAND gate is higher than the input logic threshold voltage, a voltage of L level is outputted by the inverter circuit. Further, when a minimum value of the n input voltages is equal to the input logic threshold voltage of the inverter circuit, the inverter circuit determines an intermediate value which is neither the L level nor the H level, and an output voltage of the NAND gate attains the intermediate value which is neither the L level nor the H level (this value is generally about half a value of a supply voltage of the inverter). Therefore, a boundary value of the output voltage levels H and L of the NAND gate is equal to that of the input voltage level of the inverter circuit constituting the NAND gate. This boundary value is called a logic threshold voltage V.sub.th of the NAND gate.
The operation of this arbiter circuit will then be described. Reference is also made to the FIG. 9 for the description. FIGS. 9A-D are time charts of the request signals REQ-A and REQ-B and the corresponding acknowledge signals ACK-A and ACK-B. The NAND gates 1a and 1b have the same logic threshold voltage. First, when the voltage levels of the request signals REQ-A and REQ-B are in the L level, lower than the input logic threshold voltage of the NAND gates 1a and 1b (an input voltage value corresponding to the boundary value of the output voltage level), each of the NAND gates 1a and 1b receives a voltage of the L level at its one input. Thus, the respective output voltages of the NAND gates 1a and 1b, i.e., the voltage levels of the output terminals T3 and T4 attain the H level representing negative acknowledgement. That is, neither the request signal REQ-A nor REQ-B is acknowledged in this case.
Then, when only the voltage of the request signal REQ-A attains the H level, higher than the input logic threshold voltage of the NAND gate 1a (in the time period t.sub.0 -t.sub.1 in FIGS. 9A-D), a logic level H is supplied to both input terminals 1 and 2 of the NAND gate 1a. Thus, a voltage of the L level representing acknowledgement is supplied as the acknowledge signal ACK-A to an output terminal of the NAND gate 1a, that is, the output terminal T3. Meanwhile, since a logic level L is supplied to the input terminal 4 of the NAND gate 1b, the output voltage level thereof remains in the H level. That is, only the request signal REQ-A is acknowledged in this case. Next, when the voltage of the request signal REQ-B becomes higher than the input logic threshold voltage of the NAND gate 1b to attain the H level (in the time period t.sub.1 -t.sub.2 in FIGS. 9A-D), a voltage of the H level of the request signal REQ-B is supplied to the input terminal 4 of the NAND gate 1b, while a voltage of the L level of an output of the NAND gate 1a is supplied to the other input terminal 3. Therefore, the output of the NAND gate 1b, i.e., the voltage of the acknowledge signal ACK-B attains the H level. Namely, even if the voltage of the request signal REQ-B attains the H level so as to indicate a request when the voltage of the request signal REQ-A previously attains the H level and thus its request is acknowledged, the request signal REQ-B is not acknowledged. In order to acknowledge the request signal REQ-B, the voltage level of a signal to be applied to the input terminal 3 of the NAND gate 1b, i.e., the acknowledge signal ACK-A should also attain the H level. Accordingly, the voltage level of the request signal ACK-A, which is an input signal of the NAND gate 1a, may be the L level. That is, if the request of the request signal REQ-A is completed, the request of the request signal REQ-B is acknowledged. Further, a circuit operation in case that the voltage level of the request signal REQ-A attains the H level so as to indicate a request when the voltage level of the request signal REQ-B previously attains the H level and thus its request is acknowledged, is opposite to the one described in the above case. As has been described, even though the two request signals attain the level indicating a request, the latter request signal is not acknowledged but queued until a request of the previous request signal is completed. That is, an arbitration is carried out for the contention between the two request signals.
The conventional arbiter circuit is configured as described above and thus has the following disadvantages. The following description will also be referred to FIGS. 7 and 9A-D.
When the respective voltage levels of the request signals REQ-A and REQ-B are higher than the input logic threshold voltage of the NAND gates 1a and 1b to attain the H level at the same time (the time t.sub.3 in FIGS. 9A-D), the logic level H is supplied to both input terminals of each of the NAND gates 1a and 1b. Thus, voltages at the respective output terminals of the NAND gates 1a and 1b fall lower than the logic threshold voltage of the NAND gates 1a and 1b, i.e., down to a range of the L level. Meanwhile, the NAND gate 1a receives an output of the NAND gate 1b as its input, and the NAND gate 1b receives an output of the NAND gate 1a as its input. Accordingly, the falling of the respective output voltages of the NAND gates 1a and 1b to the range of the L level means that a voltage at the one input terminal 2 of the NAND gate 1a falls to the range of the L level, and a voltage at the one input terminal 3 of the NAND gate 1b also falls to the range of the L level. If at least one of the inputs of the one NAND gate is in the L level, the output thereof tends to be the H level due to the characteristic of the NAND gate. Therefore, when the respective output voltages of the NAND gates 1a and 1b tend to fall to the L level at the same time, the output voltages are fedback to the alternate inputs of the NAND gates and thus oppositely tend to rise to the H level. Accordingly, the respective output voltages of the NAND gates 1a and 1b attain the intermediate value between the L level and the H level (at the time t.sub.3 in FIGS. 9A-D). These output voltages are fedback to the inputs of the NAND gates 1a and 1b. As described above, when the lower input voltage of the one two-input NAND gate attains a value neither the H level nor the L level, i.e., the logic threshold voltage V.sub.th, the NAND gate does not carry out the inverter operation for the lower input voltage. This state is called a metastable state. Consequently, no arbitration is carried out for the contention between the two request signals REQ-A and REQ-B.
However, it is difficult to practically manufacture the NAND gates 1a and 1b with the totally same characteristics, and thus an imbalance occurs on the characteristics of these NAND gates. That is, there is virtually a slight difference between the logic threshold voltage of the NAND gate 1a and that of the other gate 1b. Thus, the above described metastable state does not last forever, and the output voltage level of one of the NAND gates 1a and 1b (the H level or the L level) is determined some time by the logic threshold voltage of the other NAND gate to be determined. The determination of the output voltage level of one of the NAND gates causes the determination of the output voltage level of the other NAND gate which has the determined output voltage level as one of its inputs. That is, only one of the request signals REQ-A and REQ-B is acknowledged, so that the arbiter circuit is out of the metastable state. Therefore, conventionally, the imbalance between these two NAND gates, which occurs inevitably in the manufacture or is caused intentionally, renders the arbiter circuit out of the metastable state.
In the described passive method, however, the arbiter circuit inevitably has a period to be the metastable state. Therefore, a response of the acknowledge signals to the request signals delays by this period, resulting in a degradation in an access speed (in case of the DRAM) and the like. SUMMARY OF THE INVENTION
It is an object of the present invention to provide an arbiter circuit capable of rapidly arbitrating a contention.
It is another object of the present invention to provide an arbiter circuit capable of arbitrating a contention without a reduction in access time.
It is a further object of the present invention to provide an arbiter circuit being out of a metastable state in arbitration of a contention.
It is a still further object of the present invention to provide an arbiter circuit capable of rapidly outputting an acknowledge signal to acknowledge only one request signal when a plurality of request signals simultaneously attain a level indicating a request.
In order to accomplish the above described objects, the arbiter circuit according to the present invention comprises first logic circuitry for receiving a first request signal, second logic circuitry for receiving a second request signal, first buffer circuitry coupled to an output signal from the first logic circuitry, and second buffer circuitry coupled to an output signal from the second logic circuitry. The first logic circuitry is further connected to receive the output signal from the second logic circuitry and an output signal from the second buffer circuitry. The second logic circuitry is further connected to receive the output signal from the first logic circuitry and an output signal from the first buffer circuitry. When receiving a first request signal earlier than when the second logic circuitry receives a second request signal, the first logic circuitry outputs a first signal of a first logic level indicating acknowledgement of the received first request signal. When receiving the second request signal earlier than when the first logic circuitry receives the first request signal, the second logic circuitry outputs a second signal of the first logic level indicating the acknowledgement of the received second request signal. Even if receiving the second request signal while the first signal from the first logic circuitry is being outputted, the second logic circuitry outputs a signal of a second logic level different from the first level indicating the acknowledgement of the second request signal. Even if receiving the first request signal while the second signal from the second logic circuitry is being outputted, the first logic circuitry outputs a signal of the second logic level different from the first level indicating the acknowledgement of the first request signal. The first and second logic circuitry respectively output signals of a third level which is intermediate between the first and second logic levels when receiving, respectively, the first and second request signals simultaneously. The first buffer circuitry provides the signal of the first level responsive to the signal of the third level, and the second buffer circuitry outputs the signal of the second level responsive to the signal of the third level.
Since the arbiter circuit according to the present invention is thus configured, when the first and second logic circuitry receive the first and second request signals simultaneously, the signals of the third level outputted from the first and second logic circuitry are converted into different signals of the first and second levels by the first and second buffer circuitry. That is, a signal indicating the acknowledgement is outputted from only the first buffer circuitry, and thus only the first request signal is acknowledged.
According to a preferred embodiment, an input logic threshold voltage of the first buffer circuitry is lower than that of the second buffer circuitry. Such a difference between the input logic threshold voltages of the first and second buffer circuitry indicates that even in the case that output voltages of the first and second logic circuitry to be supplied respectively to the first and second buffer circuitry are identical to each other, if the identical value of the output voltages is in the range of not less than the input logic threshold voltage of the first buffer circuitry nor more than that of the second buffer circuitry, signals outputted respectively from the first and second buffer circuitry have different logic levels.
According to a further preferred embodiment, the first logic circuitry comprises a first NAND gate, and the second logic circuitry comprises a second NAND gate. The input logic threshold voltage of the first buffer circuitry is lower than a logic threshold voltage of the first NAND gate, and the input logic threshold voltage of the second buffer circuitry is higher than a logic threshold voltage of the second NAND gate. In this case, the logic threshold voltages of the first and second NAND gates respectively constituting the first and second logic circuitry are in the described range of not less than the input logic threshold voltage of the first buffer circuitry nor more than that of the second buffer circuitry. Therefore, when the respective output voltages of the first and second NAND gates are equal to each other in the above described range, signals of the different logic levels are outputted from the first and second buffer circuitry. Here, a signal voltage corresponding to the third logic level is approximately equal to the logic threshold voltages of the first and second NAND gates. Therefore, even if the first and second request signals are equally applied respectively to the first and second NAND gates constituting the respective first and second logic circuitry, different logic levels are outputted from the first and second buffer circuitry. That is, if outputs of the first and second buffer circuitry are employed as final outputs of the arbiter circuit, an arbitration is immediately carried out for a contention between two requests occurring simultaneously.
In one aspect, the arbiter circuit according to the present invention comprises a first three-input NAND gate receiving a first request signal of a logic level of the H level, a second three-input NAND gate receiving a second request signal of a logic level of the H level, a first buffer circuit receiving an output of the fist NAND gate and having a first input logic threshold voltage, and a second buffer circuit receiving an output of the second NAND gate and having a second input logic threshold voltage higher than the first input logic threshold voltage. Here, the first NAND gate is further connected to receive the output of the second NAND gate and an output of the second buffer circuit, and the second NAND gate is further connected to receive the output of the first NAND gate and an output of the first buffer circuit. The first and second NAND gates both have a logic threshold voltage between the first and second input logic threshold voltages. When an output voltage of the first NAND gate is lower than the first input logic threshold voltage, the first buffer circuit outputs, as a signal indicating acknowledgement of the first request signal, a voltage of the L level. Meanwhile, when the output voltage of the first NAND gate is higher than the first input logic threshold voltage, the first buffer circuit outputs, as a signal indicating negative acknowledgement of the first request signal, a voltage of the H level. Similarly, when an output voltage of the second NAND gate is lower than the second input logic threshold voltage, the second buffer circuit outputs, as a signal indicating acknowledgement of the second request signal, a voltage of the L level. Meanwhile, when the output voltage of the second NAND gate is higher than the second input logic threshold voltage, the second buffer circuit outputs, as a signal indicating negative acknowledgment of the second request signal, a voltage of the H level. Further, the first and second NAND gates output voltages equal to the logic threshold voltages when simultaneously receiving the first and second request signals, respectively. According to the arbiter circuit configured as described above, when the first and second NAND gates respectively receive the first and second request signals simultaneously, the first buffer circuit inevitably outputs a signal indicating negative acknowledgement of the first request signal, and the second buffer circuit inevitably outputs a signal indicating acknowledgement of the second request signal. Subsequently, when a request of the second request signal is completed, a request signal of the H logic level is applied only to the first NAND gate, so that the first NAND gate outputs a voltage lower than the first input logic threshold voltage. Consequently, the first buffer circuit outputs a signal indicating acknowledgment of the first request signal, and the second buffer circuit outputs a signal indicating negative acknowledgement of the second request signal. That is, these two "requests" which occur simultaneously are acknowledged one by one in the predetermined order of priority.
As has been described, according to the arbiter circuit of the present invention, even if voltages of the two request signals simultaneously attain the logic level indicating the "request", the entire circuit becomes the metastable state, and thus no period occurs that an arbitration cannot be carried out for the contention between the two request signals. Therefore, acknowledge signals are outputted immediately in response to inputting of the request signals. As a result, despite timing of a change in level of the two request signals, it is possible to carry out more reliable and faster arbitration than in the conventional.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.